library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pc is
	port( 
		CLK_i         : in  std_logic;
		RST_i         : in  std_logic;
		LOAD_i        : in  std_logic;
	    LOAD_DATA_i   : in  std_logic_vector(5 downto 0);
        INSTR_FETCH_i : in  std_logic;
		COUNTER_o     : out std_logic_vector(5 downto 0));
end pc;

architecture behavioral of pc is
	signal count_reg : std_logic_vector(5 downto 0);
    signal next_count : std_logic_vector(5 downto 0);

begin

    next_count <= count_reg + 1;
                  
	process (CLK_i, next_count, INSTR_FETCH_i)
	begin
		if CLK_i'event and CLK_i = '1' then
            if RST_i = '1' then
                count_reg <= (others => '0');
            elsif LOAD_i = '1' then
                count_reg <= LOAD_DATA_i;
            elsif INSTR_FETCH_i = '1' then
                count_reg <= next_count;
            end if;
		end if;
	end process;

	COUNTER_o <= count_reg;

end behavioral;

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